As the dimensions of the microelectronic devices continuously decrease in size, now into the low nm scale, the wafer surface preparation procedures play an increasingly important role in IC manufacturing. The process chemicals, sequence, and number of cleaning steps are becoming more critical in determining the desired end results. As semiconductor manufacturing continues to advance, smaller and smaller devices are being designed and built on the same wafer surface area. These fine structures have created a new set of processing issues to the fab engineers and scientists. One of these problems is selectively etching silicon nitride (Si3N4) as compared to underlying silicon oxide films.
The etching of Si3N4 is currently achieved in a variety of ways, including plasma dry etching or reactive ion etching (RIE). However, RIE of Si3N4 fails to offer high selectivity to the underlying oxide films. In addition, RIE of Si3N4 can degrade, in the form of surface pitting, the underlying film or the silicon substrate. Another existing way to etch Si3N4 is through the application of phosphoric acid (H3PO4). The use of H3PO4 has been historically used due to its high etch selectivity of Si3N4 as compared to silicon dioxide (SiO2). A typical Si3N4 etching reaction using H3PO4 can be described as follows:3Si3N4+27H2O+4H3PO4→4(NH4)3PO4+9H2SiO3 
In this reaction, water hydrolyzes Si3N4 to form hydrous silica and ammonia. The ammonia remains in solution to form ammonium phosphate. The reaction suggests that water is an integral part of the chemistry to etch Si3N4. As nitride is etched, hydrated SiO2 (H2OSiO2) is formed in the solution and inhibits the etching of SiO2, i.e. it results in a higher selectivity. The SiO2 etching continues to decrease, as shown in FIGS. 1 and 2, until the system (phosphoric acid liquid and wafers) reaches equilibrium (no mass transport), which at that time it stops. Once equilibrium is reached, an SiO2 film apparently re-deposits. The bath life will be determined depending on the tolerance that a fab can allow with this re-deposition. While this slow of oxide etch rate is beneficial (i.e. higher selectivity) but this re-deposition will cause high particle counts on the wafer which is undesirable. This phenomenon is so noticeable that it can be predicted. As shown in FIG. 2, the particle levels were in about 40 particles added up to 21×50 wafer processed in the bath after which a considerable increase in these counts was noticed.
While a number of processes have been developed in an attempt to more selectively etch Si3N4 in comparison to silicon oxides during semiconductor manufacturing, existing systems are less than optimal and suffer from a number of drawbacks. For example, in U.S. Pat. No. 6,376,261 (the '261 Patent), a system is disclosed that has a control scheme to predict the etch rate at the wafer surfaces. This system measures the thickness of a thin film on the wafers and adjusts the system parameters based on the film thickness measurements of the previous run. The adjustments are done in between wafer batches, resulting in manufacturing down time and decreased etching selectivity within each batch of wafers as the etching solution becomes contaminated and/or the concentration ratio of its components change over time. Additionally, the system disclosed in the '261 Patent requires an advanced process control system (APC) at the IC fab level.
Additional etching systems are disclosed in U.S. Pat. No. 3,715,249 (the '249 Patent), U.S. Pat. No. 6,087,273 (the '273 Patent), and U.S. Pat. No. 5,885,903 (the '903 Patent). While these systems attempt to achieve selective etching, using a mix of sulfuric and phosphoric acid, these systems do not contain a control system to ensure maximum selectivity in the etching by controlling process and mixture parameters. Thus, these systems result in decreased etching selectivity within each batch of wafers as the etching solution becomes contaminated and/or the concentration ratio of its components change over time.
In U.S. Pat. No. 5,310,457, an etching system is disclosed that utilizes the addition of HF and nitric acids to phosphoric acids to increase the etching selectivity of nitride to silicon oxide. However, the addition of HF and nitric acids to phosphoric acids has proved to be less than optimal in performance.
Finally, while some prior art etching systems and methods can achieve high selectivity in etching silicon nitride to silicon dioxide, maximization of etch selectivity is not a satisfactory sole goal. Consistent and steady etch rates for both the silicon nitride etch and the silicon oxide etch are also desirable. As mentioned above, FIG. 1 shows the results obtained from a conventional silicon nitride etch system using phosphoric acid (85% wt) at 165 C. As you can be seen, the nitride etch rate is stable while the oxide etch rate decreases with the number of wafers processed. Similar behavior is shown in FIG. 2 where the nitride and oxide etch rates were monitored against time in hours. The selectivity (i.e., the silicon nitride etch rate/silicon oxide etch rate) is plotted in FIG. 3. Because of the continuous drop in silicon oxide etch rate, the selectivity is obviously increasing with time. While this trend is a good one because it provides minimized silicon oxide loss, it also restricts the type of wafers that can be processed. Typically, wafers are soaked in the etching acid for a period of time. Thus, while the silicon nitride etch rate is fixed, the amount of silicon oxide removed will vary from lot to lot and hence the device dimensions will vary, resulting in varied performance. For obvious reasons, this is undesirable. Additionally, with continuous processing of wafers in this fashion, particles (from the etch by-products) will build up in the bath and eventually depositing on the wafers, as depicted in FIG. 4. The on-wafers particles remain at an acceptable level (<40 @0.16 um) for up to 20×50×200 mm wafers processed in the bath (1500 A were removed from each wafers). At that point, the bath needs to be drained and filled again with fresh acid to start a new processing cycle. In this scenario, it takes about 2 hours to drain/fill/heat the bath, which minimizes the utilization of the bath. Thus, the variability of etch rate is the main drawback for existing silicon nitride etch systems and methods.